Program

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8:15am – 9:00am       Breakfast & Networking

9:15am – 9:30am       Opening Remarks

9:30am – 10:30am    Keynote 1: Prof. Jason Cong

10:30am – 11:00am Coffee Break

11:00am – 12:30pm Oral Session 1: LLMs for RTL & Hardware Generation

            Total Duration: 90 Minutes 

• [Long - 15 mins] Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
• [Long - 15 mins] LACE: Large Language Model Aided Agile RISC-V Instruction Extension
• [Long - 15 mins] LLMS for Hardware-Aware Embedded Python Code Generation: Benchmark-Driven Comparative Study
• [Long - 15 mins] CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
• [Long - 15 mins] VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation
• [Short - 5 mins] LLM-Assisted Verilog Code Refinement for Efficient RTL Clock-Gating
• [Short - 5 mins] TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
• [Short - 5 mins] SynthiA: AI Agents for Automated RTL Correction and Digital Synthesis

12:30pm – 1:30pm Lunch

1:30pm – 2:30pm    Invited Session 1: Dan Fu (VP at Together, UCSD)

2:30pm – 4:00pm Oral Session 2:  Agentic Frameworks & Multi-Agent Co-Design

             Total Duration: 90 Minutes 

• [Long - 15 mins] MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design
• [Long - 15 mins] CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts
• [Long - 15 mins] Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization?
• [Long - 15 mins] CRAFT: Corrective and Robust Multi-Agent Framework for Text-to-Parametric CAD
• [Long - 15 mins] HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization
• [Short - 5 mins] RF-Agent: A Practical Framework for Building Language Agents for RFIC Design
• [Short - 5 mins] AI4OpChip: CoT-Driven LLM Agents for Integrated Circuit Design Optimization
• [Short - 5 mins] Multimodal Chip Physical Design Engineer Assistant

4:00pm – 4:30pm Coffee Break

5:30pm – 6:30pm Panel Discussion: LLM Aided Design Will Reshape the EDA Industry

        Will the next disruption in EDA come from the LLM industry itself (OpenAI etc.)?
       Will LLM aided design will shift EDA back to the era of in-house CAD in semiconductor companies since they have the data?

       Panelists: Anna Goldie (Ricursive), Brandon  Wang (Synopsis) ,  Vidya Chhabria (ASU)

6:30pm – 8:00pm Banquet Dinner

8:15am – 8:45am    Breakfast & Networking

8:45am – 9:15am    Remarks and Awards

9:15am – 10:15am Oral Session 1: Hardware Verification, Testing & Timings

              Total Duration: 90 Minutes 

• [Long - 15 mins] Are Skills Enough? An Agentic Frequency Optimization View for Large Chips
• [Long - 15 mins] VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space
• [Long - 15 mins] Breaking the Large Language Model Context Wall: Graph-Based Hardware Design Compression for Scalable Inference-Time Architectures
• [Long - 15 mins] Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code
• [Long - 15 mins] WaveformQA: Benchmarking LLM Temporal Reasoning on Digital Waveforms
• [Short - 5 mins] AutoTimer: An LLM-Powered Assistant for Timing Report Analysis and Physical Design Closure
• [Short - 5 mins] Inference-Time Scaling in Agentic Hardware Verification Workflows: A Multi-Strategy Characterization Across Protocol Complexity
• [Short - 5 mins] LLM-Aided Commit Regression Risk Ranking and Triage Using Retrieval-Augmented In-Context Learning

10:15am – 10:30am Break

10:30am – 11:30am Keynote 2

11:30pm – 1:00pm   Lunch

1:00pm – 2:00pm      Invited Session 2

2:00am – 3:30pm      Oral Session 2: Circuit Layout & Physical Design

               Total Duration: 90 Minutes

• [Long - 15 mins] Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement
• [Long - 15 mins] CHICO-Agent: An LLM Agent for the Cross-layer Optimization of 2.5D and 3D Chiplet-based Systems
• [Long - 15 mins] NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring
• [Long - 15 mins] MapTuner: Multimodal Recipe Recommendation for Physical Design with Layout Maps and Design Insights
• [Long - 15 mins] AlphaRoute: Interpretable Global Routing via SHAP-Driven Adaptive Policy and LLM-Guided Optimization
• [Short - 5 mins] Inspector: Conversational and Lightweight Analyzer of Analog Circuit Layouts Using LLM and CNNs
• [Short - 5 mins] LLM-based Early-Stage Overcurrent Protection Verification in PCB Design
• [Short - 5 mins] SpecAssess: Assessing Large Language Models in Generating RTL Design Specifications

3:30pm – 4:00pm Coffee Break

4:00pm – 5:00pm Oral Session 3: Benchmarking, Datasets & Physical Applications

              Total Duration: 60 Minutes 

• [Long - 15 mins] GenBen: A Generative Benchmark for LLM-Aided Design
• [Long - 15 mins] PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices
• [Short - 5 mins] PCBnet: A Dataset and Automatic Constructing of SPICE Netlists from Schematic Images
• [25 mins] ⭐ IEEE LAD Fellow Talk

5:00pm – 6:00pm Panel Discussion: Current LLM model architectures will never have the reasoning ability needed for HW design

        Can Current Transformer-based  LLM architectures capture HW domain design expertise (temporal and spatial reasoning) – if not where will the right architecture come from?

        Panelist: Siddarth  Garg (NYU), Ehsan Kamalinejad(Cognichip), Lindsey  Kostas(Qualcomm), Drew Wingard (Google), Caroline Trippel (Stanford University)