Awards

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LAD'25:

• Stefan Abi-Karam, Georgia Institute of Technology: Enabling Rapid Optimized Domain Acceleration With Agentic High-Level Synthesis
• Wenji Fang, Hong Kong University of Science and Technology Hong Kong SAR: Layout Logic Restructuring via Equality-Saturated Graph Retrieval-Augmented Generation
• Charles Hong, University of California, Berkeley: xComp: A Portable LLM-Driven Code Optimizer for Tensor Accelerators
• Souradip Poddar, The University of Texas at Austin: Toward Agentic Foundation Frameworks for Analog and Mixed-Signal Design Automation
• Jinwei Tang, University of Minnesota Twin Cities: GenChipUI: A Multi-Agent Framework for Trustworthy LLM-Aided Chip Design
• Zeng Wang, New York University: Do LLMs Know What’s Hard? Representation Based Difficulty and Security Estimation for Verilog Generation
• Niansong Zhang, Cornell University: Agentic and Formal RTL Optimization with LLM-Guided Equality Saturation

LAD'24

Large Language Model (LLM) for Standard Cell Layout Design Optimization 

Authors: Chia-Tung Ho, Haoxing Ren

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation 

Authors: Yongan Zhang, Zhongzhi Yu, Yonggan Fu, Cheng Wan, Yingyan Celine Lin

AMSNet: Netlist Dataset for AMS Circuits 

Authors: Zhuofu Tao, Yichen Shi, Yiru Huo, Rui Ye, Zonghang Li, Li Huang, Chen Wu, Na Bai, Zhiping Yu, Ting-Jung Lin, Lei He

LAD'25

HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design
Authors: Jinwei Tang; Jiayin Qin; Kiran Thorat; Chen Zhu-Tian; Yu Cao; Yang Zhao; Caiwen Ding

ChipXplore: Natural Language Exploration of Hardware Designs and Libraries
Authors: Manar Abdelatty; Jacob Rosenstein; Sherief Reda

Honorable Mention:
BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks
Authors: Wei Li; Yang Zou; Christopher Ellis; Ruben Purdy; Shawn Blanton; José M. F. Moura