AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL
Yunsheng Bai; Ghaith Bany Hamad; Syed Suhaib; Haoxing Ren
TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator
Deepak Vungarala; Mohammed Essa Elbtity; Kartik Pandit; Sumiya Syed; Sakila Alam; Arnob Ghosh; Ramtin Zand; Shaahin Angizi
LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits
Dimple Vijay Kochar; Hanrui Wang; Anantha Chandrakasan; Xin Zhang
Think, Prune, Train: Can Small Models Teach Themselves to Reason?
Caia Costello; Simon Guo; Anna Goldie; Azalia Mirhoseini
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
Zhongzhi Yu; Mingjie Liu; Michael Zimmer; Yingyan Celine Lin; Yong Liu; Haoxing Ren
AMSnet 2.0: A larger AMS database with AI Segmentation for Net Detection
Yichen Shi; Zhuofu Tao; Yuhao Gao; Li Huang; Wang Hongyang; Zhiping Yu; Ting Jung Lin; Lei He
MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design
Pin-Han Chen; Yu-Sheng Lin; Wei Cheng Lee; Tin-Yu Leu; Hsu Po Hsiang; Anjana Dissanayake; Sungjin Oh; Chinq-Shiun Chiu
SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
Elisavet Lydia Alvanaki; Kevin Lee; Luca Carloni
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
Zeng Wang; Minghao Shao; Jitendra Bhandari; Lakshmi Likhitha Mankali; Ramesh Karri; Özgur Sinanoglu; Muhammad Shafique; Johann Knechtel
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
Zeng Wang; Minghao Shao; Mohammed Nabeel Thari Moopan; Prithwish Basu Roy; Likhitha Mankali; Jitendra Bhandari; Ramesh Karri; Özgur Sinanoglu; Muhammad Shafique; Johann Knechtel
RTL++: Graph-enhanced LLM for RTL Code Generation
Mohammad Akyash; Kimia Zamiri Azar; Hadi Kamali
HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks
Stefan Abi-Karam; Callie Hao
Improving LLM-Powered EDA Assistants with RAFT
Luyao Shi; Michael Kazda; Charles Schmitter; Hemlata Gupta
A Dataset for LLM-Based Detection of Power-Wasters in Routed FPGA Netlists
Mohammed Bakr Sikal; Hassan Nassar; Heba Khdr; Joerg Henkel
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
Adarsh Gupta; Bhabesh Mali; Chandan Karfa
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
Ning Wang; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang; Zhe Jiang; Nan Guan
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
Ning Wang; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang; Zhe Jiang; Nan Guan
An AST-guided LLM Approach for SVRF Code Synthesis
Abanoub E. Abdelmalak; Mohamed A. Elsayed; Ilhami Torunoglu; David Abercrombie
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective
Luca Collini; Andrew Hennessee; Ramesh Karri; Siddharth Garg
DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis
Zeju Li; Changran Xu; Zhengyuan Shi; Zedong Peng; Yi Liu; Yunhao Zhou; Lingfeng Zhou; Chengyu Ma; Jianyuan Zhong; Xi Wang; Jieru Zhao; Zhufei Chu; Xiaoyan Yang; Qiang Xu
BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks
Wei Li; Yang Zou; Christopher Ellis; Ruben Purdy; Shawn Blanton; José M. F. Moura
Iceberg: Enhancing HLS Modeling with Synthetic Data
Zijian Ding; Tung Nguyen; Weikai Li; Aditya Grover; Yizhou Sun; Jason Cong
ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
Ahmed Allam; Youssef Mansour; Mohamed Shalan
HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL
Heng Ping; Shixuan Li; Peiyu Zhang; Anzhe Cheng; Shukai Duan; Nikos Kanakaris; Xiongye Xiao; Wei Yang; Shahin Nazarian; Andrei Irimia; Paul Bogdan
Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
Nicolas Dupuis; Ravi Nair; Shyam Ramji; Sean McClintock; Nishant Chauhan; Priyanka Nagpal; Bart Blaner; Ken Valk; Leon Stok; Ruchir Puri
ChipXplore: Natural Language Exploration of Hardware Designs and Libraries
Manar Abdelatty; Jacob Rosenstein; Sherief Reda
ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards
Prashanth Vijayaraghavan; Charles Mackin; Luyao Shi; Apoorva Nitsure; Ashutosh Jadhav; David Beymer; Tyler Baldwin; Ehsan Degan; Vandana Mukherjee
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
Jinghua Wang; Lily Jiaxin Wan; Sanjana Pingali; Scott Smith; Manvi Jha; Shalini Sivakumar; Xing Zhao; Kaiwen Cao; Deming Chen
OpenROAD Agent: An Intelligent Self-Correcting Script Generator for OpenROAD
Bing-Yue Wu; Utsav Sharma; Austin Rovinski; Vidya Chhabria
LATENT: LLM-Augmented Trojan Insertion and Evaluation Framework for Analog Netlist Topologies
Jayeeta Chaudhuri; Arjun Chaudhuri; Krishnendu Chakrabarty
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